Low Power High Speed Cntfet Based Differential Analog Viterbi Decoder Architecture

Differential Analog Viterbi Decoding (DAVD) for Forward-Error-Correction (FEC) is used in channel coding for digital communications. The use of analog circuits to reduce the size and power consumption of channel decoders such as Viterbi decoders has been an active area of research over the recent years. In this paper, differential analog Viterbi decoder architecture is proposed and implemented using 32 nm Carbon Nano Tube FET (CNTFET) transistors. CNTFETs can handle large currents, hence higher driving capacity and faster speed, the current mode architecture using CNTFETs further reduces number of transistors. The major computation blocks like Branch Metric Computation (BMC) and Add-Compare-Select (ACS) are implemented using CNTFET based current mirrors which reduce power and area as well as computing complexity. The differential logic operates at a maximum data rate of 500 Mbps and consumes power 65 times less than the analog Viterbi decoder. The designed decoder is suitable for low power applications.